Blade servers with multiple processors (e.g., central processing units) per blade are becoming increasingly popular as servers for commercial, scientific, and personal computing applications. The small form factor (e.g., 1 U) of such blade servers combined with the low power dissipation and high performance make these blade servers attractive for almost any computing application. Typically, a blade includes two processors and associated memory (e.g., DDR, RAMBUS, etc.). The memory control functions that were historically performed by a north bridge chip have been absorbed into the processors, eliminating the need for a separate north bridge chip and a shared system bus. Moreover, because the shared system bus has been replaced by faster point-to-point connections, the arbitration schemes that were based upon the shared system bus also have been eliminated.
Each processor typically still has a dedicated south bridge chip for handling communication between the processor and various input/output resources, such as, for example, Ethernet, EPROM, USB, PCI Express, RAID, SCSI, SATA, Firewire, etc. For example, a first processor is connected by point-to-point connections to a first south bridge, and a second processor is connected by point-to-point connections to a second south bridge. Each respective processor has access to the various resources associated with its dedicated south bridge chip, but does not have access to the resources of the other south bridge chip that is dedicated to the other processor.
Driven at least in part by a desire for general use capability, south bridge chip designers have integrated more and more features (i.e., capability of handling different resources) into current south bridge chips. A benefit of such a design paradigm is that a typical south bridge chip is robust in that it supports most, if not all, of the features required by different processing environments. A drawback of the design paradigm, however, is that the south bridge chip is oversized for any particular application because it contains more features than required by a single processor in a particular processing environment.
Component size and power dissipation are ever-present design considerations in computing architecture. As discussed above, a typical south bridge chip is oversized because it is designed to handle more features than are routinely required by a single processor in a particular processing environment. More specifically, the typical south bridge chip is physically oversized in that it occupies a greater amount of board space than would be used by a chip designed for a specific processor application. Additionally, the typical south bridge chip is oversized in its power dissipation (and, therefore, heat generation) due to the existence of so many features (even when some of the features are unused). The negative effects of increased physical size and power dissipation are compounded on a dual processor blade where each processor has a dedicated south bridge chip. With area and power being a premium in these blades, efficiently designing dual processor blades with plural dedicated south bridge chips is increasingly difficult.